B.Tech In EXTC, M.Tech in VLSI & Embedded Systems, Ph.D in VLSI Design
| From Date |
To Date |
Designation |
Organization |
Organization Address |
| 2016-03-01 |
2016-05-31 |
Assistant Professor |
St.Joseph's CET, Palai, Kottayam, Kerala |
|
| 2017-02-15 |
2020-11-20 |
Full time Ph.D Research scholar |
ANNA University, Chennai |
|
| 2020-12-18 |
2022-04-30 |
Assistant Professor |
MSEC, Sivakasi |
|
| 2022-08-01 |
2025-01-30 |
Assistant Professor |
K.J Somaiya College of Engineering, Vidyavihar, Mumbai |
|
| 2025-01-31 |
0000-00-00 |
Assistant Professor |
SIESGST |
|
| Date |
Title |
Type |
Level |
Academic Year |
| 0000-00-00 |
Power and Area Efficient Register Designs involving EHO Algorithm |
Journal |
SCI |
2020 |
| 0000-00-00 |
Design and Analysis of Power Efficient TG based Dual Edge Triggered Flip-flops with Stacking Technique |
Journal |
SCI |
August 2019. |
| 0000-00-00 |
Review of Low Power Design Techniques for Flip- flops’ |
Journal |
Scopus |
2018 |
| 0000-00-00 |
Comparison of Latches and Flip-flops in 45 nm Technology |
Journal |
|
2017 |
| 0000-00-00 |
A Low Power Highly Applicable Approach for Caches based on STT-RAM Technology |
Journal |
|
2015 |
| 0000-00-00 |
Improving the Performance of Network-on-Chip by Utilizing Fault Zone Tiling to Reuse Trace Buffers |
IEEE Conference paper |
|
2024 |
| 0000-00-00 |
Optimal Approaches for Enhancing Energy Efciency in Circuits |
Circuit Design for Modern Applications - CRC PressBook chapter |
|
2024 |
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