BE - EXTC
ME - EXTC
PhD- EXTC(Pursuing )
| From Date |
To Date |
Designation |
Organization |
Organization Address |
| 2010-10-11 |
2011-07-11 |
LECTURER |
SCOE |
Kharghar |
| 2012-07-07 |
0000-00-00 |
Assistant Professor |
SIES GST |
NERUL |
| Date |
Title |
Type |
Level |
Academic Year |
| 2014-09-30 |
EQUINOX |
Proceedings |
International |
2014-2015 |
| 2019-05-13 |
Blind Man's Eye using Raspberry PI |
Journal |
International |
2018-2019 |
| 2019-03-25 |
Adaptive Noise Elimination |
Journal |
International |
2018-2019 |
| 2023-10-10 |
Voice activated mobility wheel chair powered by solar energy |
Journal |
International |
2023-24 |
| 2023-08-23 |
Blockchain Based e-Voting System |
|
|
2023-24 |
| Date |
Title |
Presented/Published |
Level |
Academic Year |
Organizer / Venue |
| 2013-09-30 |
IMPROVEMENT IN RETURN LOSS OF HYBRID RING EQUAL POWER DIVIDER USING T EBG |
Presented And Published |
International |
2014-2015 |
Terna Engineering College
Terna College |
| Improvement In Return Loss Of Hybrid Ring Equal Power Divider Using T EBG Is Presented In Paper. |
| 2023-06-23 |
Blockchain Based e-Voting System |
Presented and Published |
|
2023-24 |
IEEE
|
|
| Date |
Title |
Type |
Level |
Role |
Venue |
| 2015-06-01 |
Attended Three Days Workshop On " Internet Of Things". |
WORKSHOP |
LOCAL |
PARTICIPANT |
SIES GST |
| 2010-07-09 |
Completed Three Days Faculty Development Workshop On " Embedded System Design Using ARM Mbed". |
WORKSHOP |
LOCAL |
PARTICIPANT |
SIES GST |
| 2018-10-25 |
Successfully Completed The NPTEL Course On “Hardware Modelling Using VERILOG †From August 2018-October 2018 |
FACULTY DEVELOPMENT PROGRAM |
NATIONAL |
PARTICIPANT |
SIES GST |
| 2017-12-26 |
Conducted Three Days Workshop On "FPGA DESIGN USING VHDL" For SE Students |
WORKSHOP |
LOCAL |
RESOURCE PERSON |
SIES GST |
| 2018-08-04 |
Conducted Three Days Workshop On "FPGA DESIGN USING VHDL" For SE Students |
WORKSHOP |
LOCAL |
RESOURCE PERSON |
SIES GST |
| 2019-12-10 |
Conducted 15 Days Internship On "FPGA DESIGN USING VHDL" For SE Students. |
WORKSHOP |
LOCAL |
RESOURCE PERSON |
SIES GST |
| 2019-01-19 |
Orientation Program Of DBMS |
OTHERS |
LOCAL |
PARTICIPANT |
Vidyalankar College , Wadala |
| 2020-05-11 |
Participated In One Week Online Faculty Development Program On “Research Methodology And Tools†Organized By Department Of Computer Engineering From 11th May To 15th May 2020. |
FACULTY DEVELOPMENT PROGRAM |
NATIONAL |
PARTICIPANT |
Online |
| 2020-05-01 |
Attended The Online Technical Session On "​HOW TO IMPROVE THE CITATION AND WRITE RESEARCH PAPERS​" Organised By Department Of Computer Engineering, Sir Visvesvaraya Institute Of Technology,Nashik On 01st May,2020. |
SEMINAR |
NATIONAL |
PARTICIPANT |
Online |
| 2020-05-04 |
Participated In One Week Online Faculty Development Program On “Scilab†Organized By Department Of Electronics & Telecommunication Engineering, S. B. Jain Institute Of Technology, Management & Research In Association With Spoken Tutorial Project, Indian Institute Of Technology Bombay Funded By National Mission On Education Through ICT, MHRD, Govt. Of India From 4th - 9th May 2020. |
FACULTY DEVELOPMENT PROGRAM |
LOCAL |
PARTICIPANT |
Online |
| 2020-06-06 |
Course on "FPGA computing System: Background Knowledge and introductory material" by coursera |
Course |
International |
Participant |
online |
| 2020-05-18 |
Completed Internship on “FPGA design and Verification†from Sandeepani School of Embedded System Design , Bangalore |
Internship |
National |
Participant |
online |
| 2021-07-23 |
Completed One month training on†VLSI SoC Design using Verilog HDL†|
Workshop (one month) |
National |
Participant |
online |
| 2021-06-30 |
Attended MHRD Online Training Sessions on “Innovation Ammbassador†Basic Level |
Workshop (one month) |
National |
Participant |
online |
| 2022-10-29 |
Completed NPTEL course on " System design using Verilog " |
Course |
National |
Participant |
online |
| 2023-01-06 |
Design for Test ( VLSI) |
Course |
National |
Participant |
online |
| 2023-08-04 |
Command Line in Linux |
Coursera course |
|
|
online |
| 2024-01-01 |
Digital system design using FPGA |
Value added course |
|
Instructor |
SIES GST |
| 2023-12-18 |
STTP on NEP -HEI |
STTP |
National |
Participant |
SIES GST |
| 2025-02-24 |
VLSI Digital Design -Chip Design and Verilog programming |
Course |
|
Participant |
Infosys Springboard |
| 2025-06-15 |
Digital system design on FPGA using Verilog |
Value added Course |
Local |
Instructor |
SIESGST |
| Academic Year |
Type |
Details |
| 2021-22 |
Copyright |
Registered Copyright on" Litter detection using Machine learning" |
| 2019-20 |
Copyright |
Registered Copyright on " H - shape Power divider using EBG " |
| 2019-2020 |
Minor Research Grant |
Real time Litter detection using Machine Learning |
| 2022-23 |
Copyright |
LORA based messenger
system for underground
miners
6754/2023-CO/L |
| 2023-24 |
Copyright |
Registered Copyright "Alert system for convulsion seizure" |
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